Indirgenmiş komut setli işlemci tasarimi

Reduced instruction set computer (RISC) processors are designed according to the principle ?simple is better.? The RISC processors are widely using in; embedded systems to work stations. Even the complex instruction computers (CISC) use RISC type micro instructions internally. This thesis presents a 32-bit pipelined reduced instruction set processor design that has 32-bit basic arithmetic, logic, control and system instructions. Most of the pipeline hazards are eliminated by hardware support. The design is modeled with VHDL (Very High Speed Integrated Circuit Hardware Description Language) hardware description language and simulated with the Mentor Graphics Corporation?s Modelsim simulator. The processor model is mapped on a low cost FPGA (Field Programmable Gate Array) chip.