Hardware design for predicting widths of values produced in microprocessors

A large percentage of the computed values in a processor are narrow values which have fewer bits compared to the width of a register. There are many techniques that improve the performance or decrease the energy consumption of the processor by exploiting narrow width values. Effective predictors that predict the widths of the produced values have been designed to improve these proposed studies. In this master thesis Direct Mapping, Full Associative Mapping, Set Associative Mapping techniques and First In First Out, Least Recently Used and Random replacement algorithms have been used during the design of these predictors. These predictors have been simulated on a Alpha microprocessor called MSIM using SPEC 2000 benchmarks and the performance of predictor designs have been compared.