NEORV32 RİSC-V işlemcisinde kayan nokta komutların desteklenmesi

The RISC-V Instruction Set Architecture (ISA) provides a customizable framework for processor design; however, the base RISC-V ISA does not have floating-point operation instructions. This necessity is addressed by integrating the F extension into the base instruction set architecture. The main objective of this thesis is to enhance the functionality of NEORV32 soft-core processor that implements only the base RISC-V ISA by incorporating F extension into its microarchitecture design. The NEORV32 soft-core processor design based on the base RISC-V ISA is first analyzed to identify the areas that can benefit from the inclusion of the F extension. The integration of the F extension into the NEORV32 soft-core processor architecture entails the implementation of all instructions in the F extension, optimizing the processor's datapath and control path, and seamless interconnectivity with the original processor design. A set of simulation techniques are employed to evaluate the performance improvements on computation speed and overall system efficiency achieved by the enhanced processor. Assembly codes incorporating floating-point instructions are generated and tested, providing insights into the benefits of the F extension integration. This thesis contributes to the advancement of soft-core processor design by enabling efficient and accurate floating-point computations through the integration of the F extension. The findings have implications for a wide range of computing systems, including embedded systems, high-performance computing clusters, and scientific simulations. These systems heavily rely on the computational accuracy and versatility offered by floating-point arithmetic, enabling complex mathematical computations, accurate physical simulations, and data analysis with high precision.