Rezonans evirgeçleri için gürültüye bağışıklı frekans kontrol döngüsü tasarımı

Resonant inverters are needed to be driven at load resonant frequency for maximum efficiency and inverter reliability. Load current oscillates with maximum amplitude at resonant frequency in a series resonant inverter. Load acts as a resistive circuit at this frequency. This is important for reliability especially working at high power regime. Because zero crossings of current and voltage waveforms happen at the same instant when circuit is driven at resonant frequency and power semiconductor switches commutates reliably. Series resonant inverters, phased-locked loops (PLL) for the frequency control purposes of resonant inverters and especially phase detectors are studied in this thesis. Driven of resonant inverters at load resonant frequency by using PLL is told and in addition to classical PLL in a frequency control loop, a novel noise immune phase detector is designed, implemented and tested. Although the PLL Chip utilized in this study (CD4046) includes a phase detector with rising edge triggered, it is found that this phase detector is not suitable for the purpose due its sensitivity to noise. It may sense additive noise as rising edge erroneously and change the output frequency. In this thesis, a new phase detector apart from the one inside the 4046 chip is tested in the frequency control loop and found more immune to electrical glitches through the experiments. The inverter malfunction problem more often than not come across during the experiments which use phase detector of PLL Chip is disappeared when the new phase detector is used. As a result of work fulfilled, the inverter got become more immune to noise and malfunction problem was disappeared by using the phase detector designed in this thesis.