Efficient FPGA implementation of soft decision demapper for digital communication systems

In digital communication systems, soft decision demapper is a digital demodulation technique which provides soft-bit values for iterative soft-in-soft-output (SISO) channel decoder. Soft-bit values provide higher decoding performance compared to hard-bit values, because of its wide decision range. In Additive White Gaussian Noise (AWGN) channel model, optimal soft-decision technique is Log-Likelihood Ratio. Although LLR provides optimal result for soft decision, it requires complex operations that increase hardware complexity. Therefore, many estimation methods have been proposed in literature as alternative to LLR. The aim of this thesis; finding and introducing the most appropriate method for soft decision demapper applications in terms of performance and computation complexity, and its efficient FPGA implementation. Towards this aim, the soft decision demapping estimation methods which proposed in literature as alternative to LLR were investigated, in terms of performance and computation complexity. Afterwards, a new soft decision demapping estimation method, which based on distance to decision boundary, was proposed for 8PSK demodulation. The proposed method was simulated using LDPC codes of IEEE 802.11n standard and negligible performance loss has been observed compared to MAX demapping technique. Finally, the proposed method was implemented on FPGA and % 85 hardware savings has been observed compared to MAX method. Consequently, the proposed soft-decision demapping method is the most suitable method for 8PSK demodulations.