Yeni nesil haberleşme sistemleri i̇çin tümleştirmeye uygun faz kaydırıcı devrelerinin tasarımı

Information sharing, dissemination of knowledge, and access to information play a major role in communication technologies. In order to ensure fast and flawless access and sharing, communication technologies are in continuous development. Today, communication technologies developed to meet these needs include Wi-Fi, LTE-M, 5G, and 6G. With the targeted advancement of these technologies, there is also a need for a broadband, low-power-consuming, and MMIC-based phase shifter. In this thesis, two different circuits are presented to the literature. Circuit I is a 3-bit digital phase shifter operating in the 4.5–5.5 GHz band, designed using a symmetric all-pass LC lattice topology. It performs 45°, 90°, and 180° phase shifting. Switching is implemented with a switched capacitor. Circuit II is designed using a symmetric-T topology operating in the 8–12 GHz band, with a diode used as the switching element. In both designs, the switching operation results in two different circuits. These circuits are named Circuit A and Circuit B. While Circuit A produces a phase shift of θA, Circuit B produces a phase shift of θB. The phase difference between these two circuits, Δθ = θB – θA, gives the total phase shift. For Circuit I, the 3-bit LC symmetric lattice design, the RMS phase errors for 45°, 90°, and 180° are 5,304°, 3,116°, and 0°, respectively; the maximum RMS insertion loss is 7.236 dB. For Circuit II, the 6-bit symmetric-T design, the RMS phase errors for 5,124°, 11,25°, 22.5°, 45°, 90°, and 180° are 0,105°, 0,185°, 0.779°, 0.768°, 1.3183°, and 2.1180°, respectively; the maximum RMS insertion loss is 2.13 dB.