Processor design with vector accelerator

Microprocessors are widely used in various fields today. In digital design applications implemented with FPGAs, processor cores are sometimes utilized. These cores can be embedded within the FPGA. For FPGAs without an embedded processor core, a processor core can be synthesized from HDL code. Such processors are referred to as soft-core processors and can operate alongside other digital design structures. Thanks to their programmable and customizable architechture, these processors simplify FPGA designs and accelerate the development process. In this thesis, a customizable 32-bit RISC-V processor design was developed using the Verilog hardware description language for FPGA applications. The designed processor can be configured to support optional RISC-V instruction extensions, such as multiplication-division, and bit-manipulations. To enhance parallel processing performance in FPGA applications, a vector accelerator that can be connected to the processor core was also integrated into the system. For observing and testing the system's outputs, UART and Timer peripherals compatible with the Wishbone protocol were designed. To facilitate the use of the developed structures, a basic C development environment and library support were provided. The system was implemented and tested in the Vivado simulation environment and on the Nexys A7-100T FPGA development board. The processor designed in the project is suitable for use in embedded systems.