Convolutional neural network design with new max pooling circuits

In this thesis, max pooling unit designs, which is an important process block of Convolutional Neural Networks (CNN), are presented. The max pooling layer is in the critical delay path of the CNN design and is important to influence the main conversion rate of a pipeline integrated circuit. The total frame processing times of the proposed designs are much shorter than the Standard Design. The proposed designs can be integrated into different pipeline structures. All designs are modeled with VHDL and synthesized on a current FPGA platform. The synthesis results show that the fastest of the proposed designs processes a 128x128 frame around 8.1 times faster than the Standard Design. The first max pooling circuit design presented in this thesis is used in the design of a fully functional pipelined CNN. The presented design has six layers. The main focus of the implementation is performance efficiency, to double the speed it divides the input images by half and simultaneously processes them in two data paths. The CNN design has reduced latency compared to a standard implementation. Also, the design fits on a medium size FPGA platform.