Novel adaptive embedded system and memory designs for low power consumption and high performance

To ensure low power consumption in modern embedded systems and computers, solutions that reduce energy dissipation are needed in Memory structures, which are the most critical part of these systems. However, these solutions are expected not to reduce the intended performance level and not cause an intolerable area cost. One of the most widely used memory structures in contemporary computer architectures is Dynamic Random Access Memory (DRAM). The bit cells that make up the DRAM can store data without access for a certain period. Still, if access is not made after a certain period of time, data is lost due to leakage currents, so it is necessary to periodically access and refresh. This process is very costly in terms of both power consumption and performance. In the scope of the thesis work, novel adaptive DRAM (Adaptive DRAM) designs (Two of the three techniques I developed; are registered with patent numbers 2019/17243 and 2019/13677, and the third one is in the registration process 2019/10444) in which DRAM can change its own circuit parameters (supply voltage or body biasing voltage) according to different conditions/inputs are proposed. Any of our proposed designs provide at least 21% lower power consumption than DRAM and only cause latency of less than 10%. In addition, our different ADRAM designs can achieve a 34% to 81.8% reduction in the total number of refreshes needed, depending on the inputs. Static Random Access Memory (SRAM) is another important branch of memory. Leakage currents in an SRAM are a growing problem due to shrinking transistor sizes (channel width, thermal loads, etc.). To solve this problem, it is proposed to design Multi-contents Aware SRAM (MASRAM), which adapts multiple cell contents and distributes this to multiple cells. MASRAM can provide a static energy dissipation reduction of up to 35% with a probability of at least 74% for a grup of cells with 64 bits (when the body biasing voltage relative to the 15th and 47th bits is applied to 64 cells), and causes an area increase of only 1%. From embedded systems to edge devices, from defense to AI applications, Field Programmable Gate Array (FPGAs) is spreading due to their reprogrammable structure, and the importance of power consumption in FPGAs is also growing. One recommended solution for low power consumption is "undervolting" in FPGAs. However, this method should not raise a reliability concern and should guarantee the intended levels of accuracy. In the scope of the thesis, the following studies were carried out for FPGA-based Convolutional Neural Networks (CNNs) accelerators: In the first study, we inspect the undervolting accuracy relationship for CNN benchmarks on different FPGAs at different frequencies. The second study is on characterizing the effect of undervolting on accuracies at different voltages under four different humidity conditions (for the first time for an FPGA), at any temperature between -40 and 50 C, under different harsh conditions. Moreover, we propose three novel reliable voltage reduction designs proposed for FPGA based CNN accelerators that provide a 65\% increase in power efficiency compared to the baseline design. In the final study, for the first time, we discover the two effects: an increasing number of CNN iterations at a low voltage decreases the accuracy (DIE), and the rejuvenating effect against DIE by temporarily applying high voltage while iteration continues at that voltage (RE). Exploiting these effects, we proposed three novel FPGA undervolting designs providing at least a 43\% power efficiency increase while preserving the desired accuracy.