Hardware acceleration of internet of things network stack with dtls support

The data communication stack on IoT devices is traditionally implemented in software as part of their operating systems. However, running computationally intensive software tasks related to network communication on a microprocessor may lead to poor application performance and high power consumption for resource-constrained IoT devices. To mitigate these issues, hardware acceleration using System on Chip (SoC) Field Programmable Gate Arrays (FPGAs) is utilized. This thesis consists of two main parts: The first part focuses on hardware acceleration of the Constrained Application Protocol (CoAP) and its underlying network protocols. The second part centers around hardware acceleration of the Datagram Transport Layer Security (DTLS) protocol, combining ASIC cryptographic accelerators with reconfigurable logic. To showcase the performance of the hardware accelerated CoAP server, both standard and secure versions are thoroughly evaluated and compared against a software-based implementation. The evaluation considers metrics such as performance, latency, power consumption, and FPGA resource utilization. Results demonstrate that the proposed CoAP hardware accelerators consume significantly less power while delivering higher performance and lower message latency compared to software-based CoAP servers. Therefore, the proposed CoAP hardware accelerator designs are viable solutions for resource-constrained IoT device deployment.