A 0.18 µm CMOS X-band low noise amplifier for space applications

Low noise amplifiers are the first and one of the most important stages of receiver systems. They are RF circuits which are widely used in many applications such as wireless systems, radio astronomy, space communications etc. Their main purpose is to amplify the weak signal at the input of the receiver by adding as little noise as possible. Since, LNAs constitute the first stage of receivers, they dominate the overall noise performance of the system. Low noise amplifier designs are mostly done using SiGe and HEMT technologies. However, low cost and better process integration of CMOS technology along with its rapidly increasing performance metrics has made it a significant contender. Mankind is exploring the space by satellites, telescopes and space crafts. These expeditions need strong support of electronics technology. Space electronics has evolved considerably over the years, however designs accomplished mostly depend on discrete elements and expensive technologies such as High Electronic Mobility Transistor (HEMT). As the space technology should get more important and prevalent in the foreseeable future, related applications require cheap, wide-spread and easily (re)producible technologies. Temperature in the outer world can get as low as 77 K and objects in space are under high radiation doses emitted by the stars and planets. Low temperature and high radiation affect the circuit performance drastically. Thus, developing designs for these extreme environments with cheap technologies is an important research problem. The main goal of this thesis is to design a 7 GHz X-band low noise amplifier for space applications using 0.18 µm UMC CMOS Mixed-Mode/RF technology. This LNA is designed for being tested at temperatures below 100 K (also called cryogenic temperatures) and radiation. Designed LNA is still at the production stage and has not been measured yet. All the results in this thesis are post-layout simulation results from Cadence and ADS tools. The classical cascode topology with inductive degeneration is used in this design. An additional bias inductance is employed to help in input impedance matching. Bias of the LNA is designated to be directly applied to the pads so that they can be changed during measurements to comply with cryogenic temperatures and radiation. Designed CMOS LNA achieves a voltage gain higher than 15 dB, 2.6 dB noise figure, –2.24 dBm IIP3 while consuming 25 mW of power.