1 MHz çıkış frekansında 80+ dB SFDR başarımı elde eden 0.18 um 16-b 32 MSPS CMOS gerilim çıkışlı sayısal-analog çevirici tasarımı

Interfacing digital domain signals to an analog control or transfer system requires an integrated circuit (IC) element referred to as a digital-to-analog converter (DAC). Achieving high precision and high dynamic linearity at high sampling speeds and high output frequencies is an ever on-going research challenge due to the complexity of interconnected tradeoffs involved in the performance of such architectures. Due to the nature of these performance tradeoffs, certain architectures are used for certain applications which prioritize 6 main parameters: physical size, power consumption, resolution, bandwidth, precision/sensitivity and cost. Most DAC architectures used in all kinds of communications, data acquisition, signal processing, and control systems can be categorized into one of two families (i) Current-mode type architectures that offer high speed at the cost of monotonicity, drift sensitivity and precision settling; (ii) Voltage-mode type architectures that address the precision settling problem but have its shortcomings in speed and resolution. This work addresses the unmet need for a precision settling, high speed and high bitrate DAC architecture by taking the standard resistor-string type buffered voltage output architecture and greatly improving its dynamic linearity for driving time-varying loads at high output frequencies. Typical operation of a resistor string-type DAC involves selecting nodes on a resistor string with a certain switching architecture dictated by the input decoder, and driving the output load through a voltage buffer. The resistor string sits between two voltage references and divides the full scale input into equal steps. DC performance of such converters is determined by the precision of the voltage references and more importantly the matching of the elements on the resistor string. These so-called static nonlinearities can be digitally calibrated to give 16-bit accuracy at low bandwidth; but error mechanisms that affect the dynamic linearity at high output frequencies remain mostly unsolved. The most fundamental dynamic performance metric of DACs is the spurious-free dynamic range (SFDR) of the output waveform. SFDR is the ratio of the root-mean-squre signal amplitude to the highest spurious component in the first Nyquist zone and is closely related to total harmonic distortion (THD) and intermodulation distortion (IMD), thus a good measure of dynamic linearity. In this work, most simulation results are presented in reference to the SFDR of the full-scale output waveform. What is considered to be the current state-of-the-art 16-bit voltage output DAC (TI-DAC8580) gives 63 dB SFDR for a 200 kHz, which is the highest frequency listed on specification. The architecture presented in this work surpasses this performance by a great amount, giving a layout extracted 83 dB SFDR for a 1 MHz signal. Six main dynamic error mechanisms were identified and compensated to achieve this performance. Code-dependent interpolating amplifier input capacitance is compensated by the inclusion of a dummy interpolating amplifier and dummy differential pair switch structure. Code-dependent resistor string equivalent resistance and code dependent Vgs and Vbs varying switch bank on-resistance are compensated with the inclusion of tap point calibration resistors. Charge injection and related glitches on the output bus are reduced by a unique fully differential resistor string and differential interpolating instrumentation amplifier architecture. Interpolating amplifier output stage nonlinearity is reduced by driving the class AB output stage transistors at their velocity saturation region. LSB sensitivity to floating resistor string loops are reduced by implementing a loop pre-charge stage on the fully differential resistor string. Aside from the development of such novel architectures, other specifics of all stages on schematic, as well as on layout, are optimized to reduce distortion by keeping the output bus settling characteristic fast and code independent. Simulation environment is chosen to be Spectre+AMS running on Cadence 6.02 evaluating BSIM4 models of the TSMC 018 um process. The unmodified standard architecture which was the starting point of this work has a 60 dB schematic level SFDR for a 1 MHz (f0), 32 MHz (fs), 2 Vpp output signal. The final design has a 88 dB schematic level SFDR, 83 dB layout level SFDR under the same conditions, tested under process corner, temperature range and supply drift variations. Tape out is expected to be April 2015.