Logic synthesis and power-delay-area modeling of nano-crossbar arrays

Self-assembled nano-crossbar arrays is one of the strong candidate for post-CMOS technology; due to its cheap and fast fabrication process on nano scale. However it needs to be researched on some topics; such as lack of logic synthesis methods and performance model. In this work, we have studied nano-arrays from different angles. Main parts of the the study are: "Logic synthesis" and "Performance Modeling". Although we have revealed most of the characteristics of the nanoarrays, there are many topics on this to study. In this work, we introduce an accurate capacitor-resistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. Although the proposed model is technology independent, we explicitly show its applicability for three different nanoarray technologies where each crosspoint behaves as a diode, a FET, and a four-terminal switch. In order to find related capacitor and resistor values, we investigate upper/lower value limits for technology dependent parameters including doping concentration, nanowire dimension, pitch size, and layer thickness. Comparison between the proposed model and a conventional simple one, which generally uses one/two capacitors for each crosspoint, demonstrates the necessity of using our model in order to accurately calculate power and delay values. The only exception where both models give approximately same results is the presence of considerably low valued resistive connections between switches. However, we show that this is a rare case for nano-crossbar technologies. After observing that performance of nano-crossbar arrays are sufficient, we study implementation of Boolean functions with crossbar nanoarrays where each crosspoint behaves as a switch. This part of the study has three main subparts "synthesis" "mathematical model" and "optimization". In the first sub-part "synthesis", we investigate nanoarray based implementation methodologies in the literature. We classify them as two-terminal or four-terminal switch based. We generalize these methodologies to be applicable for any given Boolean function by offering array size formulations. In the second sub-part "mathematical model", we have revealed the mathematical representation of four-terminal raw arrays. By doing that optimization could be turn into boolean satisfiability problem. In the third sub-part "optimization", we focus on four-terminal switch based implementations; we propose a synthesis method to implement Boolean functions with optimal array sizes. Finally, we perform synthesis trials on standard benchmark circuits to evaluate the proposed optimal method in comparison with previous nanoarray based implementation methods. The proposed synthesis method gives by far the smallest array sizes and offers a new design paradigm for nanoarray based computing architectures. Furhermore, we have also fixed "claimed" fastest optimization algorithm in the literature and compared the results.