Bir hızlı DAC' ın çıkış katı için, SRFT yöntemi ile bir geniş band empedans eşleştirici ağı tasarımı ve gerçekleştirilmesi

One of the main concerns in RF design is transferring the power between terminals with different terminations. In this regard, impedance matching networks can play a crucial role in surmounting this issue. As the master thesis, this study was therefore conducted for purpose of designing and implementation of an impedance matching network as the output stage of a high speed DAC matching 6.25Ω to 50Ω. The design was accomplished by using SRFT (Simplified Real Frequency Technique) introduced first by Prof. B. S. Yarman and H. J. Carlin in 1982. This thesis consists of six chapters, dealing with the theory of the project, the software coding process in Matlab, simulations and verification, test circuit design and realization and the integrated design in TSMC 0.180 um technology process. In the first chapter, the motivation of the study is investigated. As it is mentioned, in order design a high-speed data converter satisfying defined design goals, there is a need for a small output load which in this study is a resistor with value of 6.25 ohm. Since the value of output load is different from the standard common loads such 50 ohm or 75 ohm there is a need for an impedance matching network for avoiding power dissipation. The second chapter deals with fundamentals of the chosen approach for designing desired impedance matching network. The third chapter explains how the technique is implemented in Matlab programs. In the forth chapter, the obtained circuit from the chapter 3 is simulated by ADS Keysight simulator. Also, some realization techniques such as lumped to distributed conversions are applied during the simulations. As the next steps are about realization and measurement of the designed network, the study is focused on measurement techniques. Since all of the measuring devices such as vector network analyzers use ports with characteristic impedance of 50 ohm, for sake of straight forward measuring, two test circuits with two different techniques are designed and implemented during chapter 5. As each of the test circuits include a transformer before the designed impedance matching network and after the 50 ohm port of the measuring device, converting 50 ohm to 6.25 ohm . Chapter 6 tries out the integrated version of the design. In this regard, the TSMC 180 um technology process is used. During this chapter the design is implemented with component models presented in RF library. Although the design is successful in maintaining the transducer power gain's wav form but it fails illustrate good results in gain; giving a lossy network.