Biyolojik sinir sistemlerinin modellenmesi ve gerçeklenmesi

The elementary processing units of brain are the nerve cells, or neurons. Neurons are believed to be the key elements in signal processing. Those cells are analog units that work together to carry out the highly sophisticated computations in cognition and control. In traditional artificial neural networks, the neuron behavior is described only in terms of firing rate, but most of the real neurons, commonly known as spiking neurons, transmit information by pulses called action potentials or spikes. Spiking neuron models vary from the computationally simple Integrate and Fire (I&F) model to biologically meaningful Hodgkin-Huxley (HH) model. The network constructed with those models are called Spiking Neural Network (SNN). According to accuracy requirements and electronically easeness of implementation the appropriate model is selected for implementing the network. Today, SNN's has become essential to study the brain functions for Artificial Network Community. In this thesis, a new dynamical neuron model suitable for low power and compact VLSI implementation is presented. This model can operate in biological time and voltage scale. When designing the model, geometrical nullcline approach is used. In operational area, model has similar nullclines with INa,p+IK model resulting to equivalency in dynamic behaviour at subthreshold region. Offered model has two state variables such that one represents the membrane voltage while the other one represents the recovery variable. Also it has after spike reset mechanism as in hybrid models. Unlike Izhikevich and AdEx I&F model, only the membrane voltage is reset to a constant reset value after the spike reaches its apex. This is a big advantage of the model since implementing the hard reset of recovery variable requires large number of transistors which is a limiting factor for design of large-scale neuromorphic hardware. Recovery variable grows to the desired 'after-spike' value on its own in our model. Tangent hyperbolic characteristic of nullcline slows down the growth speed of state variable while approaching to the positive (or negative) saturation region of tangent hyperbolic. So this mechanism limits the growth speed as it will result to realistic spike timing. Even the new neuron model seems to have ten different parameters when it is scaled to obtain the minimum numbers of parameters it is seen that it has only four independent parameters and an input current. One can obtain nearly all of the major spiking templates of real biological neurons by only modifiying two of this parameters and input current. A software application in MATLAB to examine the neuro computational features of new neuron model with numerical simulations is developed, also. This application has a GUI for accepting the inputs from user and displaying the calculated outputs. By using this application it is shown that the model is capable of generating the most of the spiking patterns exhibited by the known types of neocortical and thalamic neurons when the proper parameter set is selected. New neuron model is constructed with tangent hyperbolic functions since it is odd symetric and easily implementable as VLSI circuit by using subthreshold CMOS technique. Judicious use of this technique leads to a very effective low power CMOS neuron. Implemented neuron circuit consist of a single first-order log domain filter, hyperbolic function generators, linear voltage dividers, compare & reset block and a voltage tunable current reference. In design phase, the simulation results are fitted to analytic expressions by using linear least squares curve fitting method. Accuracy metric of fitting is Root Mean Squared Error (RMSE) value. The design parameters is iterated until RMSE value stays below a spesific value. This technique is named as Iterative Curve Fitting Method (ICFM). Long tailed circuit topology with cascode output stage is used for implementing the tangent hyperbolic function generators (THB). To minimize the effect of process parameters deviation, a core THB with minimum tail current supplied from matched 100pA current source is designed, then the output is multiplied by a constant value for obtaining the real output of different THB's. Linear voltage divider circuit consist of two layered ladder type diode connected NMOS transistors. Dividing ratio of this block is determined as 8.8. When compared with the conventional MOS voltage dividers offered configuration has the advantage of having less number of transistors for the same divider value and of reduced body effect. Source shifting or offset voltage is applied to this circuit since it operates at very low currents. Log domain filter is a current mode circuit such that it is completely suitable for the implementation of recovery variable of our neuron model. Source shifting is applied to this circuit, also. A comparator circuit which drives a discharge switch is designed. Comparator circuit is implemented by connecting the input of two stage inverter to the output of a simple long tailed circuit that acts as differential amplifier. Tail current of differential amplifier should be high enough to drive output inverter stage as fast as possible. Thus this current is selected 2.3 nA. Discharge switch is implemented with big sized NMOS transistor since it should have high current sink capacity. Process parameter deviation and temperature dependency are the two most critical problems effective on the circuit operation. Especially for the circuits based on subthreshold operation, temperature dependency is a very common problem. Therefore, a wide temperature range voltage tunable current reference circuit is implemented. Voltage tuning is needed for minimizing the effect of process parameters deviation. The tuning voltage values that guarantees the proper operation of neuron circuit at all process corners are obtained. Initial design and simulations are carried out with TSMC 0.18 micron technology by using LTSpice design tools. Then all the blocks of neuron circuit is designed again with AMS 0.35 micron SiGe-BiCMOS process by using Cadence® Virtuoso® tools for both verifying the previous design and implementing the Layout of the neuron. The circuit topology and transistor sizes are kept same as in TSMC design and obtained the same results by only modifiying the value of voltage, currents sources and capacitors. The operating and supply voltages is shifted to higher values since the transistor transconductance of AMS technology is quite lower than TSMC technology. Minimum channel width to length ratio is selected as 2 micron/2 micron at both designs for minimizing the effect of the absolute parameter deviation in sizing caused by the VLSI manufacturing process. AMS design occupies 0.0128 mm2 chip area. Power consumption is 277.5 nW for AMS design and 241 nW for TSMC design. Supply and offset voltages are 2.5 V and 0.5 V for AMS circuit, 1.5 V and 0.2 V for TSMC circuit, respectively. Spiking patterns obtained from circuit simulations perfectly matches with numerical results. In most of the synapse models, temporal dynamics are neglected and synapses are assumed as an instantaneous multiplier operator. A realistic model should take into consideration the spatial and temporal summation of synaptic currents. In the light of these observations, a new dynamical synapse model for coupling the neurons to create the realistic SNNs is offered. This model consist of similar terms as new neuron model that makes it also suitable for compact and low power VLSI implementation. The model allows to make a synapse excitatory or inhibitory by only altering the reversal potential parameter. Synchronized activity of neurons take role in a wide range from cognitive functions to rhythmic movements of animals. The phase response curve (PRC), i.e. the neurons's response to weak perturbations, is a useful tool to understand the collective dynamical properties of a neuron in a network. Therefore the PRC of new neuron with VLSI implemented parameters is extracted and shown that it has Type II PRC. Based on complete neuron and synapse models, synchronization behavior of different number of reciprocally connected neurons that form a ring coupled network with excitatory and inhibitory synapses is studied. Numerical simulations are accomplished and inphase, antiphase and N-phase synchronization behaviour for networks with 2, 3 and 4 neurons are observed. VLSI circuit of two reciprocally coupled neuron and a ring coupled network with 3 neurons is designed by using TSMC 0.18 micron technology. Because of weak coupling synaptic currents are so small to implement as VLSI circuit. So some scaling operations are made to shift the synapse circuit output current value in a VLSI implementable range. At circuit simulations the expected inphase, antiphase and N-phase synchronization patterns is successfully observed. Power consumption is 282 nW for two reciprocally coupled neuron and 320 nW for three ring coupled neuron network.